On a semiconductor substrate are formed a plurality of sense amplifier circuits associated with respective bit lines each connected to a plurality of memory cells in which either binary data value is stored. When one of the memory cells commonly connected to a bit line is accessed during read mode, the voltage level of the bit line is varied to a certain voltage level depending upon the binary data stored therein, and the certain voltage level appearing on the bit line is then applied to the associated sense amplifier circuit together with a reference voltage level, typically, having an intermediate voltage level between the voltage levels of the two binary data for quick judgement of the binary data read, out from the accessed memory cell.
A typical example of a known sense amplifier circuit incorporated in a dynamic random access memory device is illustrated in FIG. 1. The dynamic random access memory device is provided with a plurality of word lines and a plurality of bit lines arranged in rows and columns. However, only two of the word lines and two of the bit lines are shown in FIG. 1, and are indicated by reference numerals 1, 1A, 2 and 2A, respectively. To the bit line 2 are commonly connected a plurality of memory cells one of which is indicated by reference numeral 3 and comprises an n-channel MOS transistor 6 and a storage capacitor 7 capable of storing either binary data value in the form of a voltage level. The memory cell 3 is provided between the bit line 2 and the ground and gated by the decoded address signal appearing on the word line 1. To the bit line 2A are also connected a plurality of memory cells one of which is indicated by reference numeral 8 and similarly comprises an n-channel MOS transistor 9 and a storage capacitor 10. The bit lines 2 and 2A are paired and connected to respective sense nodes N1 and N2 of a sense amplifier circuit (indicated by a broken line). Whenever one of the memory cells connected to the bit line 2A is accessed, the bit line 2 is supplied from a reference voltage source 11 with a reference voltage of, typically, an intermediate voltage level between the voltage levels of the two binary data values. On the other hand, the bit line 2A is electrically connected to a reference voltage source 12 so that the reference voltage appears on the bit line 2A whenever the stored binary data is read out from the a selected memory cell to the bit line 2.
Turning to FIG. 2 which shows waveforms of signals in the sense amplifier circuit illustrated in FIG. 1, operations of the conventional sense amplifier circuit will be described on the assumption that the memory cell 3 storing the binary data of 1 is accessed. Prior to decoding a set of address signals applied to the address pins of the dynamic random access memory device, a precharging signal .PHI.1 remains high and is applied to n-channel MOS transistors 13, 14, 15, 16 and 17. The precharge transistors 13 and 14 are provided between the sense nodes N1 and N2 and a positive voltage source Vdd, respectively, and the precharge transistors 15 and 16 are, on the other hand, provided between control nodes N3 and N4 and the positive voltage source Vdd. The precharge transistors 13, 14, 15 and 16 thus connected are applied with the precharging signal .PHI.1, then the precharge transistors 13, 14, 15 and 16 turn on, supplying the sense nodes N1 and N2 and the control nodes N3 and N4 with a positive voltage of a certain level. When the sense node N1 and N2 are pulled up to the certain level, the voltages of the bit lines 2 and 2A also go up to the certain level and balance with each other through the transistor 17 which is concurrently turned on by the precharging signal .PHI.1.
After the precharging signal .PHI.1 goes down at time t.sub.1, the address signals applied to the decoder circuit from the address pins are decoded, and the voltage of the word line 1 then rises for turning the MOS transistor 6 on at time t.sub.2. When the MOS transistor 6 is turned on, the precharged bit line 2 is electrically connected to the storage capacity 7 through the MOS transistor 7. However, the storage capacitor 7 storing the binary data of 1 has been charged to a voltage level approximately equal to the certain level on the bit line 2, so that the substantial fluctuation does not take place on the bit line 2. When the word line 1 is selected, the digit line 2A is unconditionally connected to the reference voltage source 12 and then goes down to the intermediate voltage level. Thus, the paired bit lines 2 and 2A have different voltages and put a differential voltage of about 0.1 volt between the sense nodes N1 and N2 because different voltages are supplied from the paired bit lines 2 and 2A.
After the differential voltage appears on the sense nodes N1 and N2 based on the different voltages supplied from the paired bit lines 2 and 2A, a first clock signal .PHI.2 goes up at time t.sub.3 and then an n-channel transistor 18 turns on by the action of the first clock signal .PHI.2. When the active transistor 18 is turned on, a current path is established between a common node N5 and the ground, thus pulling the common node down to the ground level. This causes a pair of cross coupled n-channel transistors 19 and 20 to simultaneously turn on with different channel conductances. Namely, the transistor 19 has a gate connected to the sense node N2 having the relatively low intermediate voltage level, then the channel is formed in the transistor 19 with a relatively small channel conductance. On the other hand, the transistor 20 has a gate connected to the sense node N1 having the relatively high voltage level, then the channel is produced in the transistor 20 with a relatively large channel conductance. The channels thus produced in the respective transistors 19 and 20 are different in channel conductance so that the voltage levels on the sense nodes N1 and N2 go down at different respective speeds, thus amplifying the differential voltage between the sense nodes N1 and N2. This results in a voltage level on the sense node N1 slightly lower than the certain voltage level and in a voltage level on the sense node N2 approximately equal to the ground level, as will be seen from the waveforms in FIG. 2.
The sense amplifier circuit illustrated in FIG. 1 further has a pair of cross coupled n-channel transistors 21 and 22 provided between the sense nodes N1 and N2 and the control nodes N3 and N4, respectively. The gates of the transistors 21 and 22 are cross coupled to the sense nodes N2 and N1. Therefore, the transistor 21 has a channel with a relatively small conductance but the transistor 22 has a channel with a relatively large conductance, thereby pulling the voltages of the control nodes N3 and N4 down to respective voltage levels corresponding to those on the sense nodes N1 and N2. This also results in a voltage level on the sense node N3 slightly lower than the certain voltage level and in a voltage level on the sense node N4 approximately equal to the ground level. The control nodes N3 and N4 are connected to pull-up capacitors 23 and 24, respectively. If a second clock signal .PHI.3 goes up to a preselected positive voltage level at time t.sub.4, the control node N3 goes up over the positive voltage level Vdd to a certain high level which causes an n-channel transistor 25 to fully turn on, thereby supplying the sense node N1 with the positive voltage level Vdd. As the control node N4 has the voltage level approximately equal to the ground level, the control node N4 remains below the supply voltage level Vdd, thereby maintaining the transistor 26 in the off condition. The transistor 26 being thus in the off condition, the sense node N2 still remains in the voltage level approximately equal to the ground level as will be seen from the waveform thereof in FIG. 2. In this manner, the initial differential voltages of about 0.1 volt is amplified, and the binary data stored in the memory cell 3 is judged and read out based thereon.
The first and second clock signals .PHI.2 and .PHI.3 concurrently go down to the low levels at time t.sub.5 so that the active transistor 18 turns off and the control node N3 goes down to the previous certain voltage level lower than the supply voltage level Vdd. This results in the transistor 25 being turned off. After the turning off of the transistor 25, the precharging signal .PHI.1 rises again to cause the MOS transistors 13, 14, 15, 16 and 17 to turn on at time t.sub.6, so that the sense nodes N1 and N2 and the control nodes N3 and N4 are precharged to the certain level from the supply voltage level Vdd for preparation of subsequent read out cycle. The precharging signal .PHI.1 applied to the transistor 17 causes the transistor to turn on for balancing of the sense nodes N1 and N2.
The conventional sense amplifier circuit, however, has a drawback in that unbalance in voltage level tends to take place and, for this reason, the sense amplifier circuit sometimes obtains undesirable results which do not reflect the initial differential voltage. This results from the fact that the control nodes N3 and N4 have different voltage levels prior to their precharging, and are independently precharged through the respective transistors 15 and 16 supplied with the precharging signal .PHI.2. The control nodes N3 and N4 thus having the different voltage levels are then saturated to the certain voltage level at different times and need a long period of time to balance with each other as will be understood from the waveforms in FIG. 2. As a result of the independent precharging, the unbalance in voltage is liable to take place on the control nodes N3 and N4. In addition, the precharging signal .PHI.1 typically has a voltage level approximately equal to the supply voltage level Vdd, so that the period of time needed tends to be prolonged. During the above described long period of time, if a fluctuation of the supply voltage level Vdd takes place, the fluctuation may promote the unbalance on the control nodes N3 and N4. The sense nodes N1 and N2 are supplied with a small differential voltage of, for example, 0.1 volt so that any inbalance between the control nodes N3 and N4 has significant influence on the small differential voltage, and inverts the relation of the magnitude of the voltage levels on the sense nodes N1 and N2 in some cases.
The present invention contemplates elimination of these drawbacks which have thus far been inherent in the conventional sense amplifier circuit.